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charger flash mcu HT45F5Q revision: v1.10 date: de ? e ?? e ? 1 ?? ? 01 ? de ? e ?? e ? 1 ?? ? 01 ?
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu table of contents eates cpu featu ? es ......................................................................................................................... ? pe ? iphe ? al featu ? es ................................................................................................................. ? gene?al des??iption ........................................................................................ 7 blo?k diag?a? .................................................................................................. 7 pin assign?ent ........... ..................................................................................... 8 pin des??iption .......... ...................................................................................... 8 a?solute maxi?u? ratings .......................................................................... 10 d.c. cha?a?te?isti?s ....................................................................................... 10 a.c. cha?a?te?isti?s ........................................................................................ 11 adc ele?t?i?al cha?a?te?isti?s ... ................................................................. 1? lvd&lvr ele?t?i?al cha?a?te?isti?s ............................................................ 1? dac ele?t?i?al cha?a?te?isti?s ... .................................................................. 1? op amplifer electrical characteristics clo ? king and pipelining ......................................................................................................... 1 ? p ? og ? a ? counte ? ................................................................................................................... 17 sta ? k ..................................................................................................................................... 17 a ? ith ? eti ? and logi ? unit C alu ........................................................................................... 18 flash p?og?a? me?o?y ................................................................................. 19 st ? u ? tu ? e ................................................................................................................................ 19 spe ? ial ve ? to ? s ..................................................................................................................... 19 look-up ta ? le ............. ........................................................................................................... 19 ta ? le p ? og ? a ? exa ? ple ........................................................................................................ ? 0 in ci ?? uit p ? og ? a ?? ing ......................................................................................................... ? 1 on-chip de ? ug suppo ? t C ocds ......................................................................................... ?? ram data me?o?y ......................................................................................... ?? st ? u ? tu ? e ................................................................................................................................ ?? gene ? al pu ? pose data me ? o ? y ............................................................................................ ?? spe ? ial pu ? pose data me ? o ? y ............................................................................................. ??
rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu special function register description ........................................................ 25 indi ? e ? t add ? essing registe ? s C iar0 ? iar1 ......................................................................... ? 5 me ? o ? y pointe ? s C mp0 ? mp1 .............................................................................................. ? 5 bank pointe ? C bp ................................................................................................................. ?? a ?? u ? ulato ? C acc ............................................................................................................... ?? p ? og ? a ? counte ? low registe ? C pcl .................................................................................. ?? look-up ta ? le registe ? s C tblp ? tblh ................................................................................ ?? status registe ? C status .................................................................................................... ? 7 eeprom data memory ........... ....................................................................... 29 eeprom data me ? o ? y st ? u ? tu ? e ........................................................................................ ? 9 eeprom registe ? s ............ .................................................................................................. ? 9 reading data f ? o ? the eeprom ........................................................................................ ? 1 w ? iting data to the eeprom ................................................................................................ ? 1 w ? ite p ? ote ? tion ..................................................................................................................... ? 1 eeprom inte ?? upt ............. ................................................................................................... ? 1 p ? og ? a ?? ing conside ? ations ............. ................................................................................... ?? oscillator ........................................................................................................ 33 os ? illato ? ove ? view ............. .................................................................................................. ?? system clock confgurations ................................................................................................ ?? inte ? nal rc os ? illato ? C hirc ............. .................................................................................. ? 4 inte ? nal ?? khz os ? illato ? C lirc ........................................................................................... ? 4 supple ? enta ? y os ? illato ? ...................................................................................................... ? 4 operating modes and system clocks ......................................................... 35 syste ? clo ? ks ...................................................................................................................... ? 5 syste ? ope ? ation modes ...................................................................................................... ?? cont ? ol registe ? .................................................................................................................... ? 7 ope ? ating mode swit ? hing ................................................................................................... ? 9 stand ? y cu ?? ent conside ? ations ........................................................................................... 4 ? wake-up ................................................................................................................................ 4 ? watchdog timer ........... .................................................................................. 44 wat ? hdog ti ? e ? clo ? k sou ?? e .............................................................................................. 44 wat ? hdog ti ? e ? cont ? ol registe ? ............. ............................................................................ 44 wat ? hdog ti ? e ? ope ? ation ................................................................................................... 45 reset and initialisation .................................................................................. 46 reset fun ? tions ............. ....................................................................................................... 4 ? reset initial conditions ......................................................................................................... 49 input/output ports ......................................................................................... 52 pull-high resisto ? s ................................................................................................................ 5 ? po ? t a wake-up ............. ........................................................................................................ 5 ? i/o po ? t cont ? ol registe ? s ..................................................................................................... 5 ? pin-sha ? ed fun ? tions ............. ............................................................................................... 54 i/o pin st ? u ? tu ? es .................................................................................................................. 55 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 5 ?
rev. 1.10 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 5 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu timer module C tm ........................................................................................ 57 int ? odu ? tion ........................................................................................................................... 57 tm ope ? ation ............. ........................................................................................................... 57 tm clo ? k sou ?? e ............. ...................................................................................................... 57 tm inte ?? upts ......................................................................................................................... 57 tm exte ? nal pins ................................................................................................................... 58 tm input/output pin cont ? ol registe ? ................................................................................... 58 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 59 standard type tm C stm .......... .................................................................... 60 standa ? d tm ope ? ation ............. ............................................................................................ ? 0 standa ? d type tm registe ? des ?? iption ............................................................................... ? 0 standa ? d type tm ope ? ating modes .................................................................................... ? 4 analog to digital converter .......... ................................................................ 73 a/d ove ? view ............. ........................................................................................................... 7 ? a/d conve ? te ? registe ? des ?? iption ...................................................................................... 74 a/d conve ? te ? data registe ? s C sadol ? sadoh ............. ................................................... 74 a/d conve ? te ? cont ? ol registe ? s C sadc0 ? sadc1 ? pasr ............. .................................... 74 a/d ope ? ation ....................................................................................................................... 7 ? a/d conve ? te ? input signal ................................................................................................... 77 conve ? sion rate and ti ? ing diag ? a ? .................................................................................. 77 su ?? a ? y of a/d conve ? sion steps ............. .......................................................................... 78 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 79 a/d t ? ansfe ? fun ? tion ............. .............................................................................................. 79 a/d p ? og ? a ?? ing exa ? ples ................................................................................................. 80 battery charge module .......... ....................................................................... 82 batte ? y cha ? g ing constant cu ?? ent and constant voltage modes ........................................ 8 ? ocp and ovp fun ? tions ...................................................................................................... 8 ? batte ? y cha ? ge module registe ? s ......................................................................................... 8 ? digital to analog conve ? te ? ................................................................................................... 84 operational amplifer 0 .......................................................................................................... 85 interrupts ........................................................................................................ 87 inte ?? upt registe ? s ................................................................................................................. 87 inte ?? upt ope ? ation ................................................................................................................ 90 exte ? nal inte ?? upt ............. ...................................................................................................... 91 multi-fun ? tion inte ?? upt .......................................................................................................... 9 ? a/d conve ? te ? inte ?? upt ......................................................................................................... 9 ? ti ? e base inte ?? upts ............................................................................................................. 9 ? eeprom inte ?? upt ............. ................................................................................................... 9 ? tm inte ?? upts ......................................................................................................................... 94 ocvp inte ?? upt ............. ......................................................................................................... 94 inte ?? upt wake-up fun ? tion ................................................................................................... 94 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 95
rev. 1.10 4 de?e??e? 1?? ?01? rev. 1.10 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu low voltage detector C lvd .......... ............................................................... 96 lvd registe ? ............. ............................................................................................................ 9 ? lvd ope ? ation ....................................................................................................................... 97 application circuit ......................................................................................... 98 instruction set ................................................................................................ 99 int ? odu ? tion ........................................................................................................................... 99 inst ? u ? tion ti ? ing .................................................................................................................. 99 moving and t ? ansfe ?? ing data ............................................................................................... 99 a ? ith ? eti ? ope ? ations ............................................................................................................ 99 logi ? al and rotate ope ? ation ............................................................................................. 100 b ? an ? hes and cont ? ol t ? ansfe ? ........................................................................................... 100 bit ope ? ations ..................................................................................................................... 100 ta ? le read ope ? ations ....................................................................................................... 100 othe ? ope ? ations ............. .................................................................................................... 100 instruction set summary .......... .................................................................. 101 ta ? le conventions ............................................................................................................... 101 instruction defnition ................................................................................... 103 package information .................................................................................... 112 1 ? -pin nsop (150 ? il) outline di ? ensions .......................................................................... 11 ?
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 7 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu features cpu features ? operating voltage: f sys = 8mhz: 2.2v~5.5v ? up to 0.5s instruction cycle with 8mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? two oscillators: internal rc -- hirc internal 32khz -- lirc ? fully intergrated internal 8mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 6-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 2k14 ? ram data memory: 648 ? true eeprom memory: 328 ? watchdog timer function ? up to 8 bidirectional i/o lines ? single pin-shared external interrupts ? one timer modules for time measure, compare match output, capture input, pwm output, single pulse output functions (10-bit stm1) ? dual time-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? battery charge circuit build-in o cp and ovp circuits (h/w protection) opa 2 for voltage and current sense 8-bit dac ? low voltage reset function ? low voltage detect function ? package type: 16-pin nsop
rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu general description th e ht4 5 f5 q is an assp mcu specifcally designed for battery charger applications. offering u ser s the convenience of flash memory multi-programmin g featur es, the device also includes a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter function. multiple and extremely flexible timer mod ules pro vide ti ming, pu lse ge neration, ca pture in put, co mpare ma tch ou tput, single pulse output and pwm generation functions. protective features such as an internal watchdog timer and low voltage reset coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure tha t the dev ice wil l fnd exc ellent use in app lications such as el ectronic me tering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. block diagram 8-?it risc mcu co?e i/o ti?e? module flash p?og?a? me?o?y eeprom data me?o?y flash/eeprom p?og?a??ing ci??uit?y ram data me?o?y ti?e bases low voltage reset wat?hdog ti?e? low voltage dete?t inte??upt cont?olle? reset ci??uit inte?nal rc os?illato?s 1?-?it a/d conve?te? ove? cu??ent p?ote?tion ove? voltage p?ote?tion batte?y cha?ge ci??uit
rev. 1.10 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 9 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu pin assignment cp0n pa4/stp0 pa?/stck0/[int] pa7/int/res/stp0i pa5/[int]/[stp0]/a1p a1x a1n senseln 1? 15 14 1? 1? 11 10 9 1 ? ? 4 5 ? 7 8 vsense pa?/an?/[int] pa?/an?/ocdsck/icpck pa1/an1/vref pa0/an0/ocdsda/icpda vdd/avdd vss/avss isense HT45F5Q/ht45v5q 16 nsop-a note : 1. bracketed pin names indicate non-default pinout remapping locations. 2. a vdd&vdd means the vdd and a vdd are the double bonding. vss&a vss means the vss and a vss are the double bonding. 3. the ocdsda and ocdsck pins are the ocds dedicated pins pin description with the exception of the power pins and some relevant transformer control pins, all pins on this device can be referenced by their port name, e.g. p a0, p a1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pin name function op i/t o/t description pa0/an0/ ocdsda/ icpda pa0 pawu papu pasr st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an0 sadc0 pasr an adc input ? hannel ocdsda st cmos ocds add ? ess/data line ? fo ? ev ? hip only. icpda st cmos icp add ? ess/data line pa1/an1/ vref pa1 pawu papu pasr st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an1 sadc0 pasr an adc input ? hannel vref pasr an adc ? efe ? en ? e voltage input pa ? /an ? / ocdsck/ icpck pa ? pawu papu pasr st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an ? sadc0 pasr an adc input ? hannel ocdsck st ocds ? lo ? k line ? fo ? ev ? hip only. icpck st icp ? lo ? k line pa ? /an ? /[ int] pa ? pawu papu pasr st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an ? sadc0 pasr an adc input ? hannel int pasr ifs0 st exte ? nal inte ?? upt
rev. 1.10 8 de?e??e? 1?? ?01? rev. 1.10 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu pin name function op i/t o/t description pa4/stp0 pa4 pawu papu pasr st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. stp0 pasr st cmos stm output pa5/[ int]/ [stp0]/a1p pa5 pawu papu pasr st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. int pasr ifs0 st exte ? nal inte ?? upt stp0 pasr st cmos stm output a1p st opa1 positive exte ? nal input pin pa ? / stck0/[int] pa ? pawu papu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. stck0 st stm ? lo ? k input int ifs0 st exte ? nal inte ?? upt pa7/int/ stp0i/res pa7 pawu papu rstc st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. int ifs0 rstc st exte ? nal inte ?? upt stp0i rstc st cmos stm input res rstc st exte ? nal ? eset input a1x a1x an opa1 output a1n a1n an opa1 negative input sensein sensein an opa1 signal input isense isense an cu ?? ent sense input vsense vsense an voltage sense input cp0n cp0n an ocp negative input vdd vdd pwr digital positive powe ? supply avdd avdd pwr analog positive powe ? supply vss vss pwr digital negative powe ? supply avss avss pwr analog negative powe ? supply lenged: i/t: input type o/t: output type op: optional by register option pwr: power st: schmitt t rigger input cmos: cmos output an: analog pin *: vdd is the device power supply while a vdd is the adc power supply . the a vdd pin is bonded together internally with vdd. **: vss is the device ground pin while a vss is the adc ground pin. the a vss pin is bonded together internally with vss.
rev. 1.10 10 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 11 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i ol t otal .............. ................................................................................................... .................... 80ma i oh t otal .............. ...................................................................................................................... -80ma total power dissipation .............. ........................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hirc) f sys =8mhz ? . ? 5.5 v i dd ope ? ating cu ?? ent (hirc) ? v no load ? all pe ? iphe ? als off ? wdt ena ? le ? lvr ena ? le ? opa ena ? le ? ocp/ovp ena ? le f sys = f hirc = 8mhz 0.8 ? .0 ? a 5v 1.5 ? .0 ? a ope ? ating cu ?? ent (lirc) ? v no load ? all pe ? iphe ? als off ? opa ena ? le ? ocp/ovp ena ? le f sys = f lirc = ?? khz 0. ? 5 1. ? ? a 5v 0.5 ? 1. ? ? a i idle idle0 mode stand ? y cu ?? ent (lirc) 5v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? opa ena ? le ? ocp/ovp ena ? le 0.47 1.0 ? a idle1 mode stand ? y cu ?? ent (hirc) 5v no load ? adc off ? wdt ena ? le ? f sys =8mhz on ? opa ena ? le ? ocp/ovp ena ? le 0.89 ? .0 ? a i sleep sleep0 mode stand ? y cu ?? ent (lirc off) 5v no load ? adc off ? wdt disa ? le ? lvr disa ? le ? opa ena ? le ? ocp/ovp ena ? le 0.4 ? 1.0 ? a sleep1 mode stand ? y cu ?? ent (lirc on) 5v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? opa ena ? le ? ocp/ovp ena ? le 0.47 1.0 ? a v il input low voltage fo ? i/o po ? ts ex ? ept res pin 5v 0 1.5 v 0 0. ? v dd v input low voltage ( res) 0 0.4v dd v v ih input high voltage fo ? i/o po ? ts ex ? ept res pin 5v ? .5 5 v 0.8v dd v dd v input high voltage ( res) 0.9v dd v dd v i ol i/o sink cu ?? ent ? v v ol =0.1v dd 1 ? ? 0 ? a 5v 40 ? 8 ? a i oh i/o sou ?? e cu ?? ent ? v v oh =0.9v dd -4 -8 ? a 5v -8 -1 ? ? a r ph pull-high resistan ? e ? v ? 0 ? 0 100 n 5v 10 ? 0 50 n
rev. 1.10 10 de?e??e? 1?? ?01? rev. 1.10 11 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu a.c. characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions f sys syste ? clo ? k (hirc) ? . ? ~5.5v f sys = f hirc = 8mhz 8 mhz syste ? clo ? k (lirc) f sys = f lirc = ?? khz ?? khz f hirc syste ? clo ? k (hirc) ? v/5v ta = ? 5c - ? % 8 + ? % mhz ? v/5v ta = 0c to 70c -5% 8 +5% mhz ? . ? v~5.5v ta = 0c to 70c -8% 8 +8% mhz ? . ? v~5.5v ta = -40c to 85c -1 ? % 8 +1 ? % mhz f lirc syste ? clo ? k (lirc) ? . ? v~5.5v ta = -40c to 85c 4 ?? 80 khz t tc stm input pin mini ? u ? pulse width 0. ? s t res exte ? nal reset mini ? u ? low pulse width 10 s t int exte ? nal inte ?? upt mini ? u ? pulse width 0. ? s t eerd eeprom read ti ? e ? 5 t sys t eewr eeprom w ? ite ti ? e ? 5 ? s t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt ? f sys off at halt ? reset pin reset) f sys = f h ~ f h / ? 4 ? f h = f hirc 10 1 ? ?? t hirc f sys = f sub = f lirc ? t lirc syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt ? f sys on at halt state) f sys = f lirc 1 ? 5 t sys t rstd syste ? reset delay ti ? e (por reset ? lvr ha ? dwa ? e reset ? lvr softwa ? e reset ? wdt softwa ? e reset ? reset cont ? ol registe ? softwa ? e reset) 10 50 100 ? s syste ? reset delay ti ? e (reset pin reset ? wdt ti ? e- out ha ? dwa ? e cold reset) 10 1 ? .7 50 ? s 1rwh w sys i sys pdd dd i d d it d s dsd 9 d 966 d d d y d s
rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu adc electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage ? .7 5.5 v v adi input voltage 0 v ref /v dd v v ref refe ? en ? e voltage ? .0 v dd v dnl diffe ? ential non-linea ? ity ? v/5v v ref =av dd =v dd t ad =0.5s/10s - ? + ? lsb inl integ ? al non-linea ? ity ? v/5v v ref =av dd =v dd t ad =0.5s/10s -4 +4 lsb i adc additional cu ?? ent fo ? adc ena ? le ? v no load ? t ad =0.5s 1.0 ? .0 ? a 5v no load ? t ad =0.5s 1.5 ? .0 ? a t adck clo ? k pe ? iod 0.5 10 s t on ? st adc on to adc sta ? t 4 s t ads sa ? pling ti ? e 4 t adck t adc a/d conve ? sion ti ? e (in ? lude sa ? ple and hold ti ? e) 1 ? t adck lvd&lvr electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage v lvr 5.5 v v lvr low voltage reset voltage lvr ena ? le -5% ? .1 +5% v v lvd low voltage dete ? tion voltage en lvd=1 ? v lvd = ? .0v -5% ? .0 +5% v en lvd=1 ? v lvd = ? . ? v -5% ? . ? +5% v en lvd=1 ? v lvd = ? .4v -5% ? .4 +5% v en lvd=1 ? v lvd = ? .7v -5% ? .7 +5% v en lvd=1 ? v lvd = ? .0v -5% ? .0 +5% v en lvd=1 ? v lvd = ? . ? v -5% ? . ? +5% v en lvd=1 ? v lvd = ? . ? v -5% ? . ? +5% v en lvd=1 ? v lvd =4.0v -5% 4.0 +5% v v bg bandgap refe ? en ? e voltage -5% 1.09 +5% v i op ope ? ating cu ?? ent 5v lvd ena ? le ? lvr ena ? le ? vbgen =0 ? 0 ? 5 a 5v lvd ena ? le ? lvr ena ? le ? vbgen =1 ? 00 ? 00 a t bgs v bg tu ? n on sta ? le ti ? e 150 s t lvds lvdo sta ? le ti ? e fo ? lvr ena ? le ? vbgen = 0 ? lvd off on 15 s fo ? lvr disa ? le ? vbgen = 0 ? lvd off on 150 s t lvr low voltage width to reset ? 8 ? 40 ? 40 s
rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu dac electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage ? . ? 5.5 v v daco output voltage range v ss v dd v i dac a/d conve ? te ? refe ? en ? e voltage 5v 110 500 a ote dac v oltage formula 8 8[7 : 0] 2 dd dac v ? ? ? ? ? ? ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions d.c. characteristic v dd ope ? ating voltage ? . ? 5.5 v v os input offset voltage 5v without ? ali ?? ation (anof[4:0] = 10000b) -15 +15 ? v with ? ali ?? ation -4 +4 ? v i source output cu ?? ent 5v inp=1v ? inn=0v ? v out =4.5v ? 5 ? v i sink 5v inp=0v ? inn=1v ? v out =0.5v 5 7 ? v v cm input co ?? on mode range 5v v ss v dd - 1.4 v a.c. characteristics a ol open loop gain 5v ? 0 80 db sr slew rate 5v no load 0. ? v/s gbw op gain bandwidth 5v v cm =v dd -1.4 r l =1m,c l =100pf 1 ? mhz
rev. 1.10 14 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 15 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ovp electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v ddc ovp ope ? ating voltage 4. ? 5.5 v i ddc ovp ope ? ating cu ?? ent 5v ?? .5 a v cmpos co ? pa ? ato ? input offset voltage 5v -15 15 ? v v hys hyste ? esis width ? 0 40 ? 0 ? v v cm input co ?? on mode range v ss v dd - 1.4 v ovpd vsense ove ? voltage dete ? tion 5v - ? % ? v + ? % v 1rwh 7kh ?9? prgxoh lv lwhjudjhg zlwk d frpsdudwru dg wkh lwhudo 9 yrowdjh lv surylghg wr wkh frpsdudwru hjdwlyh 7kh ?9?' yhul fdwlr sxusrvh lv wkd w zkh 9vhvh lv pruh wkd 9 wkh frp sdudwru rxwsxw v kljk ohyho rwkhuzlvh orz ohyho ocp electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v ddc ocp ope ? ating voltage 4. ? 5.5 v i ddc co ? pa ? ato ? ope ? ating cu ?? ent 5v ? 00 a v cmpos co ? pa ? ato ? input offset voltage 5v -15 15 ? v v hys hyste ? esis width ? 0 40 ? 0 ? v v cm input co ?? on mode range v ss v dd - 1.4 v
rev. 1.10 14 de?e??e? 1?? ?01? rev. 1.10 15 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu power good characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v det dete ? tion voltage - ? % 4. ? v + ? % v i ddc powe ? good ope ? ating cu ?? ent 5v 85 a t pds powe ? good output sta ? le ti ? e 1 ? 5 ? 50 500 s power on reset electrical characteristics ta=25?c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr vdd v dd rising rate to ensu ? e powe ? -on reset 0.0 ? 5 v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s
rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 17 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications clocking and pipelining the main system clock, derived from either a hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? system clock and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 17 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc10~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced . this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.
rev. 1.10 18 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 19 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu sta?k pointe? sta?k level ? sta?k level 1 sta?k level ? : : : sta?k level ? p?og?a? me?o?y p?og?a? counte? botto? of sta?k arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.10 18 de?e??e? 1?? ?01? rev. 1.10 19 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu flash program memory the program memory is the location where the user code or program is stored. for this device the program memory are flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, this flash device of fers users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 2k14 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. 000h initialisation ve?to? 004h 7 ffh 14 ?its inte??upt ve?to?s 01 ch 0?0h program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h i s re served fo r u se b y t his d evice re set fo r p rogram i nitialisation. aft er a d evice r eset i s initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp . this register defnes the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd c [m] or t abrdl[m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu

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? table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the t abrd c [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd c [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address ; is referenced to the last page or present page mov tblp,a : : tabrd c tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd c tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 705h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 se ? ial data/add ? ess input/output icpck pa ? se ? ial clo ? k vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and ground. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.
note: * may be resistor or capacito r. the resistance of * must be great er than 1k or the capacitance of * must be less than 1nf.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu on-chip debug support C ocds there is an ev chip named ht45v5 q which is used to emulate the ht45f5 q device. this ev chip device also provides an on-chip debug function to debug the device during the development process. the ev chip and the actual mcu device are almost functionally compatible except for the on-chip de bug func tion. use rs c an use t he e v c hip de vice t o e mulate t he re al c hip de vice behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pi ns in the actual mcu de vice will ha ve no ef fect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on- ? hip de ? ug suppo ? t data/add ? ess input/output ocdsck ocdsck on- ? hip de ? ug suppo ? t clo ? k input vdd vdd powe ? supply gnd vss g ? ound
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h. spe?ial pu?pose data me?o?y gene?al pu?pose data me?o?y 00h ?fh 40h 7fh bank 1 bank 0 eec in bank 1 data memory structure general purpose data memory there i s 6 4 b ytes o f g eneral p urpose d ata m emory wh ich a re a rranged i n b ank 0 a nd b ank1. al l microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later . it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h.
rev. 1.10 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu 00h iar 0 01h mp 0 0?h iar 1 0?h mp 1 04h 05h acc 0?h pcl 07h tblp 08h tblh 09h 0 ah status 0 bh 0 ch 0 dh 0 eh 0 fh 10h dacc 11h sensw 1?h 19h mfi 0 18h 1 bh 1 ah 1 dh 1 ch 1 fh 1?h 14h 15h 1?h 17h : unused ; read as 00h a0 vos ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ??h ?4h ?5h ??h ?7h 1 eh pgdr bank 0 bank 1 ?0h ?1h ??h ??h ?4 h~? fh pac papu bp integ intc 0 intc 1 pawu dac 8 smod tbc eea sadc 1 sadoh sadc 0 rstc pasr stm 0 dl stm 0 dh lvdc pa wdtc smod 1 eed sadol stm 0c0 stm 0c1 stm 0 al stm 0 ah chrgen 40h eec ifs 0 special purpose data memory structure
rev. 1.10 ?4 de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start : m ov a , 04h ; setup size of block m ov block , a m ov a , offset adres1 ; accumulator loaded with frst ram address m ov mp0 , a ; setup memory pointer with frst ram address loop : c lr iar0 ; clear the data at address defned by mp0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu bank pointer C bp for this device, the data memory is divided into two banks, bank0 and bank1. selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addre ssing the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank1 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 na ? e dmbp0 r/w r/w por 0 bit 7 ~ 1 unimplemented, read as "0" bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tblh these two special function registers are used to control operation of the look-up table which is stored in the program memory . tblp is the table pointer and indicate the location where the table data is located. its value must be setup before any table read commands are executed. its value can b e c hanged, f or e xample u sing t he inc o r dec i nstructions, a llowing f or e asy t able d ata pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu status register bit 7 6 5 4 3 2 1 0 na ? e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x x unknown bit 7~6 unimplemented, read as 0 bit 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu eeprom data memory this device contains an area of internal eeprom data memory . eeprom, which stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. by incorporating this kind of d ata m emory, a wh ole n ew h ost o f a pplication p ossibilities a re m ade a vailable t o t he d esigner. the a vailability o f e eprom st orage a llows i nformation su ch a s p roduct i dentifcation n umbers, calibration values , s pecifc us er data, s ystem s etup data or other product information to be s tored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 328 bits for this device. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using one address register and one data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address registers, eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be direct ly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d4 d ? d ? d1 d0 eed d7 d ? d5 d4 d ? d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 na ? e d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~ 5 unimplemented, read as 0 bit 4~0 d 4~d0 : data eeprom address data eeprom address bit 4 ~ bit 0
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu eed register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 na ? e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should als o frs t be cleared before implementing any write operat ions, and then set agai n aft er the write cyc le has start ed. note that setting the wr bi t high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global, eeprom interrupt are enabled and the stack is not full, a subroutine call to the eeprom interrupt vector , will take place. when the eeprom interrupt is serviced, the eeprom interrupt fag def will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples ? reading data from the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom write clr bp mov a, eed ; move read data to register mov read_data, a ? writing data to the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a clr emi set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bitC executed immediately after ; set wren bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom write clr bp
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. t wo f ully i ntegrated i nternal o scillators, r equiring no extern al components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillator p rovides h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillator . with t he c apability of dyna mically swi tching be tween fa st a nd sl ow syst em c lock, t his de vice ha s the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. inte ? nal high speed rc hirc 8mhz inte ? nal low speed rc lirc ?? khz oscillator types system clock confgurations there are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a l ow spee d oscillator. the high speed oscillator is the internal 8mhz rc oscillato r. the low speed oscillator is the intern al 32khz rc oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. hirc p?es?ale? f h lirc low speed os?illation f h /? f h / 1? f h / ?4 f h /8 f h /4 f h / ?? hlclk cks?~cks 0 ?its f sys f l high speed os?illation system clock confgurations
rev. 1.10 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as a f ixed f requency o f 8 mhz. de vice t rimming d uring t he manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised . as a result, at a power supply of 5v and at temperature of 25 ?c degrees, the fxed oscillation frequency of the hirc will have a tolerance within 2%. internal 32khz oscillator C lirc the i nternal 3 2khz sy stem osc illator i s t he l ow f requency o scillator. i t i s a f ully i ntegrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. supplementary oscillator the low speed oscillator , in addition to providing a system clock source is also used to provide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts.
rev. 1.10 ?4 de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks this device has two dif ferent clock sources for both the cpu and peripheral function operation. by providing the user with clock options using register programming, a clock system can be confgured to obtain maximum application performance. the m ain syst em c lock, c an c ome fro m e ither a hi gh fre quency, f h , or a l ow fre quency, f l , a nd i s selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from hirc oscillator . the low speed system clock source can be sourced from the internal clock f l . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there is one additional internal clock for the peripheral circuits, the t ime base clock, f tbc . f tbc i s sourced from the lirc oscillator . the f tbc clock is used as a source for the t ime bas e interrupt functions and for the tm. hirc p?es?ale? f h lirc low speed os?illation f h /? f h / 1? f h / ?4 f h /8 f h /4 f h / ?? hlclk cks?~cks 0 ?its f sys f lirc high speed os?illation wdt f sys /4 f tb ti?e base 0 ti?e base 1 tbck f l f tbc idlen system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its own special c haracteristics a nd whi ch c an be c hosen a ccording t o t he spe cific pe rformance a nd power requirements of the application. there are two modes allowing normal operation of the microcontroller, t he nor mal mo de a nd sl ow mo de. t he r emaining f our m odes, t he sl eep0, sleep1, idle0 and idle1 modes are used when the microcontroller cpu is switched of f to conserve power. operating mode description cpu f sys f lirc f tbc normal ? ode on f h ~f h / ? 4 on on slow ? ode on f l on on idle0 ? ode off off on on idle1 ? ode off on on on sleep0 ? ode off off off off sleep1 ? ode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of it s functi ons operati onal and where the system clock is provide d the high speed oscil lator. this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the h igh sp eed o scillator hi rc. t he h igh sp eed o scillator wi ll h owever fr st b e d ivided b y a r atio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from the low speed osci llator lirc. running the micro controller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f lirc clock will be stopped too, and the w atchdog t imer function is disabled. sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f lirc clocks will continue to operate if the w atchdog t imer function is enabled. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer and tm. in the idle0 mode, the system oscillator will be stopped.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer and tm. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode, the w atchdog t imer clock, f lirc , will be on. control register a single register, smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 na ? e cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 bit 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0 bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode, but after a wake-up has occurred the fag will change to a high level after 1~2 cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on.
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power . smod1 register bit 7 6 5 4 3 2 1 0 na ? e fsyson rstf lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown bit 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as 0 bit 3 rstf : reset caused by rstc setting 0: not active 1: active this bit can be clear to 0, but cannot s et to 1.if this bit is s et, only cleared by software or por reset. bit 2 lvrf : lvr function reset fag 0: not active 1: active this bit can be clear to 0, but can not be set to 1. bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu
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operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically al lowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the smod1 register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tm.
rev. 1.10 40 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 41 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se tting t he hlclk bit to 0 and setting the cks2~cks0 bits to 000 or 001 in the smod register .this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
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rev. 1.10 40 de?e??e? 1?? ?01? rev. 1.10 41 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, w here the high s peed s ystem os cillator is us ed, the h lclk bit s hould be s et to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked.
? ? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? - ?? ? entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and f lirc clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped as the wdt is disabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.10 4 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 4? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f lirc clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt is enabled and its clock source is selected to come from the f lirc clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in smod1 register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the f lirc clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f lirc clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in smod1 register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and f lirc clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f lirc clock. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.10 4? de?e??e? 1?? ?01? rev. 1.10 4 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the enabled lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.10 44 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 45 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer c lock sourc e i s prov ided by t he i nternal f lirc c lock wh ich i s suppl ied by t he lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer tim eouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v . however , it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the wdt can be enabled/disabled using the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. the wrf software reset fag will be indicated in the smod1 register . these registers control the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 na ? e we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 we4 ~ we0 : wdt function software control 10101: wdt disable 01010: wdt enable other values: reset mcu when thes e bits are changed to any other values by the environmental noise to reset the microcontrolle r, the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit will be set to 1to indicate the reset source. bit 2~ 0 ws2 ~ ws0 : wdt t ime-out period selection 000: 2 8 / f lirc 001: 2 9 /f lirc 010: 2 10 /f lirc 011: 2 11 /f lirc (default) 100: 2 12 /f lirc 101: 2 13 /f lirc 110: 2 14 /f lirc 111: 2 15 /f lirc these three bi ts de termine the di vision rat io of the w atchdog t imer sourece clock, which in turn determines the timeout period. smod1 register bit 7 6 5 4 3 2 1 0 na ? e fsyson rstf lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown bit 7 fsyson : f sys control in idle mode 0: disable 1: enable
rev. 1.10 44 de?e??e? 1?? ?01? rev. 1.10 45 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu bit 6~4 unimplemented, read as 0 bit 3 rstf : reset caused by rstc setting 0: not active 1: active this bit can be clear to 0, but cannot s et to 1.if this bit is s et, only cleared by software or por reset. bit 2 lvrf : lvr function reset fag 0: not active 1: active this bit can be clear to 0, but can not be set to 1. bit 1 unimplemented, read as 0 bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. w ith regard to the w atchdog t imer enable/disable function, there are fve bits, we4~we0, in the wdtc register to additional enable/disable and reset control of the w atchdog t imer. we4 ~ we0 bits wdt function 10101b disa ? le 01010b ena ? le any othe ? value reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. four methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a value other than 01010b and 10101b is written into the we4~we0 bit locations, the second is an external hardware reset, which means a low level on the external reset pin, the third is using the w atchdog t imer software clear instruction and the fourth is via a hal t instruction. there is only one method of using software instruction to clear the watchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 15 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 8ms for the 2 8 division ration.
rev. 1.10 4 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 47 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu clr wdtinst?u?tion 8-stage divide? wdt p?es?ale? we4~we0 ?its wdtc registe? reset mcu f lirc f lirc /? 8 8-to-1 mux clr ws?~ws0 wdt ti?e-out (? 8 /f lirc ~ ? 15 /f lirc ) haltinst?u?tion lirc res pin ?eset watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in a ddition t o t he p ower-on r eset, si tuations m ay a rise wh ere i t i s n ecessary t o f orcefully a pply a reset condition when the microcontroller is running. one example of this is where after power has be en a pplied a nd t he m icrocontroller i s a lready ru nning, t he res l ine i s fo rcefully pu lled l ow. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
rev. 1.10 4? de?e??e? 1?? ?01? rev. 1.10 47 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu res pin reset although t he m icrocontroller ha s a n i nternal rc re set func tion, i f t he v dd powe r suppl y ri se t ime is not fas t enough or does not s tabilise quickly at pow er-on, the internal res et function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay , normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up t imer. for most applicati ons a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to t he res p in sho uld b e k ept a s sho rt a s p ossible t o m inimize a ny st ray n oise i nterference. fo r applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. note: * it is recommended that this component is added for added esd protection ** it is recomm ended that this component is added in environments where power line noise is signifcant external res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. note: t rstd is power-on delay, typical time=16.7ms res reset timing chart
rev. 1.10 48 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 49 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ? rstc external reset register bit 7 6 5 4 3 2 1 0 na ? e rstc7 rstc ? rstc5 rstc4 rstc ? rstc ? rstc1 rstc0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 rstc7 ~ rstc0 : pa7/ res selection 01010101: confgured as pa7 pin or other function 10101010: confgured as res pin other v alues: mcu reset (reset will be active after 2~3 lirc clock for debounce time) all reset will reset this register as por value except wdt time out hardware warm reset. low voltage reset C lvr the mi crocontroller cont ains a low volt age reset circuit in order to moni tor the supply volt age of the device and provide an mcu reset should the value fall below a certain predefned level. the lvr func tion i s a lways e nabled duri ng t he norm al a nd sl ow m odes wi th a spe cifc l vr vol tage v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when c hanging t he ba ttery, t he l vr wi ll a utomatically re set t he de vice i nternally a nd t he l vrf bit in the smod1 register will also be set to1. for a valid l vr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specified in the l vr characteristics. if t he l ow vol tage st ate does not e xceed t his va lue, t he l vr wi ll i gnore t he l ow supply voltage and will not perform a reset function. the actual v lvr is 2.1v , the l vr will reset the device after 2~3 lirc clock cycles. note that the l vr function will be automatically disabled when the device enters the sleep/idle mode. note:t rstd is power-on delay, typical time=50ms low voltage reset timing chart ? smod1 register bit 7 6 5 4 3 2 1 0 na ? e fsyson rstf lvrf wrf r/w r/w r/w r/w r/w por 0 0 x 0 x unknown bit 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as 0 bit 3 rstf : reset caused by rstc setting 0: not active 1: active this bit can be clear to 0, but cannot s et to 1.if this bit is s et, only cleared by software or por reset. bit 2 lvrf : lvr function reset fag 0: not active 1: active this bit can be clear to 0, but can not be set to 1. bit 1 unimplemented, read as 0
rev. 1.10 48 de?e??e? 1?? ?01? rev. 1.10 49 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog time-out reset during normal operation the w atchdog tim e-out reset during normal operation is the same as an l vr reset except that the watchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing normal o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing normal o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins ? ounting ti ? e ? modules ti ? e ? modules will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs sta ? k pointe ? sta ? k pointe ? will point to the top of the sta ? k
rev. 1.10 50 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 51 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know wh at c ondition t he m icrocontroller i s i n a fter a p articular r eset o ccurs. t he f ollowing t able describes how each type of reset af fects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the lar ger package type. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* p ? og ? a ? counte ? 000h 000h 000h 000h 000h mp0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu mp1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu bp ---- --0 ---- --0 ---- --0 ---- --0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu smod 000- 0011 000- 0011 000- 0011 000- 0011 uuu- uuuu lvdc --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu integ ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuu- mfi0 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs0 ---- --00 ---- --00 ---- --00 ---- --00 ---- -uuu wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 0011 -111 uuuu Cuuu smod1 0--- 0x-0 0--- uu-u 0--- uu-u 0--- uu-u u--- uu-u integ ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu eea ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu eed 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu sadol (adrfs=0) xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- sadol (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu sadc0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu sadc1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu rstc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu pasr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0c0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0c1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0dl 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.10 50 de?e??e? 1?? ?01? rev. 1.10 51 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* stm0dh ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu stm0al 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0ah ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu chrgen 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu dac8 1000 0000 1000 0000 1000 0000 1000 0000 uuuu uuuu dacc 1--- ---- 1--- ---- 1--- ---- 1--- ---- u--- ---- sensw --01 0101 --01 0101 --01 0101 --01 0101 --uu uuuu a0vos 0001 0000 0001 0000 0001 0000 0001 0000 uuuu uuuu pgdr ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u eec ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: "*" stands for warm reset "-" not implement "u" stands for "unchanged " "x" stands for "unknown"
rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 5? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provide bidirectional input/output lines labeled with port name p a. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o control register list register name bit 7 6 5 4 3 2 1 0 pa pa7 pa ? pa 5 pa 4 pa ? pa ? pa 1 pa 0 pac pa c7 pac ? pac 5 pac 4 pac ? pac ? pac 1 pac 0 papu pa pu7 papu ? papu 5 papu 4 papu ? papu ? papu 1 papu 0 pawu pa wu7 pawu ? pawu 5 pawu 4 pawu ? pawu ? pawu 1 pawu 0 pasr pas7 pas ? pas5 pas4 pas ? pas ? pas1 pas0 ifs0 intps1 intps0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selecte d using register p apu, and are implemented using weak pmos transistors. note that only when the i/o ports are configured as digital intput or nmos output, the internal pull-high func tions c an be e nabled usi ng t he p apu re gister. in ot her c onditions, i nternal pul l-high functions are disabled. papu register bit 7 6 5 4 3 2 1 0 na ? e pa pu7 papu ? papu 5 papu 4 papu ? papu ? papu 1 papu 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit 7~ bit 0 pull-high control 0: disable 1: enable
rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. note that only when the port a pins are confgured as general purpose i/os and the device is in the halt s tatus, the p ort a w ake-up functions can be enabled us ing the relevant bits in the p awu register. in other conditions, the wake-up functions are disabled. pawu register bit 7 6 5 4 3 2 1 0 na ? e pa wu7 pawu ? pawu 5 pawu 4 pawu ? pawu ? pawu 1 pawu 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac, to control the input/output confguration. with these control registers, each cmos output or input can be reconfgured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 na ? e pa c7 pac ? pac 5 pac 4 pac ? pac ? pac 1 pac 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input
rev. 1.10 54 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 55 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for these pins, the desired function of the multi-functio n i/o pins is selected by a series of registers via the application program control. pin-shared function selection registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the device includes p asr and ifs0 registers which can select the desired functions of the multi-function pin-shared pins. the m ost i mportant p oint t o n ote i s t o m ake su re t hat t he d esired p in-shared f unction i s p roperly selected and also deselected. t o select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register . after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. t o correctly desele ct the pn-shared function, the peripheral function should frst be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. pasr register bit 7 6 5 4 3 2 1 0 na ? e pas7 pas ? pas5 pas4 pas ? pas ? pas1 pas0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas7~pas6 : pin-shared control bits 00: pa5/int 01: stp0 10: pa5/int 11: a1p bit 5 pas5 : pin-shared control bit 0: pa4 1: stp0 bit 4 pas4 : pin-shared control bit 0: pa3/int 1: an3 bit 3 pas3 : pin-shared control bit 0: pa2 1: an2 bit 2~1 pas2~pas1 : pin-shared control bits 00: pa1 01: pa1 10: vref 11: an1 bit 0 pas0 : pin-shared control bit 0: pa0 1: an0
rev. 1.10 54 de?e??e? 1?? ?01? rev. 1.10 55 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ifs0 register bit 7 6 5 4 3 2 1 0 na ? e intps1 intps0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 intps1, intps0 : int pin remapping control 00: int on pa7 (default) 01: int on pa3 10: int on pa5 11: int on pa6 i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure
rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 57 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure programming considerations within the user program, one of the frs t things to consider is port initialisation. after a res et, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input stat e, the level of whi ch de pends on the ot her connected circuitry and whe ther pull - high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data regis ters are frst programmed. selecting which pins are inputs and which are outputs can be achieved byt e-wide by l oading t he c orrect va lues i nto t he a ppropriate port c ontrol re gister or by programming i ndividual bi ts i n t he port c ontrol re gister usi ng t he set [m ].i a nd clr [m ].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 57 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu timer module C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the device includes only one t imer m odule, abbreviated to the name tm. the tm is multi-purpose timing unit and serves to provide operations such as t imer/counter, input capture, compare match output and single pulse output as well as being the function al unit for the generation of pwm signals. this tm has two individual interrupts. the addition of input and output pins for this tm ensures that users are provided with timing units with a wide and fexible range of features. introduction the device contains only one standard t ype tm unit, with its individual reference name, tm, and its type is 10-bit stm. the main features of tm are summarised in the accompanying table. function stm ti ? e ? /counte ? i/p captu ? e co ? pa ? e mat ? h output pwm channels 1 single pulse output 1 pwm align ? ent edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod tm function summary tm operation the t m of fers a di verse ra nge of func tions, from si mple t iming ope rations t o pw m si gnal generation. t he k ey t o u nderstanding h ow t he t m o perates i s t o se e i t i n t erms o f a f ree r unning counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator , known as a compare match s ituation, a tm interrupt s ignal w ill be generated w hich can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the st0ck2~s t0ck0 bits in the s tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external stck0 pin. the stck0 pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the standard type tm has two internal interrupts, the internal compara tor a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin.
rev. 1.10 58 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 59 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu tm external pins the t m ha s t wo t m i nput pi ns, wi th t he l abel s tck 0 a nd s tp 0 i. t he t m i nput pi n s tck 0 , is essentially a clock source for the tm and is selected using the s t0ck2~ s t0ck0 bits in the s tm0c0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the st0ck2~s t0ck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the other tm input pin, s tp0i, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the s t0io1 and s t0io0 bits in the s tm0c1 register. the t m ha s one out put pi n wi th t he l abel s tp0. w hen t he t m i s i n t he com pare ma tch out put mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a c ompare m atch sit uation oc curs. t he e xternal s tp0 out put pi n i s a lso t he pi n where t he t m generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , w ith a s ingle bit in each register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. stm stp0 stck0 captu?e input tck input output stp0i stm function pin control block diagram
rev. 1.10 58 de?e??e? 1?? ?01? rev. 1.10 59 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu programming considerations the tm counter registers and the capture/compare ccra register , and ccrp register pair for periodic t imer module, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra register and ccrp registers are implemented in the way shown in the following diagram and accessing the register is carried out ccrp low byte register using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values. data bus 8-?it buffe? stm0dh stm0dl stm0ah stm0al stm ccra registe? (read/w?ite) stm counte? registe? (read only) the following steps show the read and write procedures: ? writing data to ccra ? step 1. w rite data to low byte stm0al C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte stm0ah C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra ? step 1. read data from the high byte stm0dh, stm0ah C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte stm0dl, stm0al C this step reads data from the 8-bit buffer.
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can be controlled with two external input pins and can drive one external output pin. tm type tm name tm input pin tm output pin 10- ? it stm stm stck0 ? stp0i stp0 f sys f sys /4 f h /?4 f h /1? f tbc f tbc stck0 000 001 010 011 100 101 110 111 st0ck?~st0ck0 10-?it count-up counte? ?-?it co?pa?ato? p ccrp ?7~?9 ?0~?9 10-?it co?pa?ato? a st0on st0pau co?pa?ato? a mat?h co?pa?ato? p mat?h counte? clea? 0 1 output cont?ol pola?ity cont?ol pin cont?ol stp0 st0oc st0m1? st0m0 st0io1? st0io0 stma0f inte??upt stmp0f inte??upt st0pol pasr ccra st0cclr edge dete?to? stp0i st0io1? st0io0 standard type tm block diagram standard tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal clock source. there are also tw o internal comparators w ith the names , comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. t he ccrp is 3-bit wide whose value is compared with the highest 3 bits in the counter while the ccra is the 10 bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the st0on bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the standard t ype tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources and can also control an output pin. all operating setup conditions are selected using relevant internal registers. standard type tm register description overall operation of the standard tm is controlled using series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stm0c0 st0pau st0ck ? st0ck1 st0ck0 st0on st0rp ? st0rp1 st0rp0 stm0c1 st0m1 st0m0 st0io1 st0io0 st0oc st0pol st0dpx st0cclr stm0dl d7 d ? d5 d4 d ? d ? d1 d0 stm0dh d9 d8 stm0al d7 d ? d5 d4 d ? d ? d1 d0 stm0ah d9 d8 10-bit standard tm register list
rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu stm0c0 register bit 7 6 5 4 3 2 1 0 na ? e st0pau st0ck ? st0ck1 st0ck0 st0on st0rp ? st0rp1 st0rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 st0pau : stm counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal c ounter ope ration. w hen i n a pa use c ondition t he st m wi ll rem ain powe red up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. bit 6~4 st0ck2~st0ck0 : select stm counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: stck0 rising edge clock 111: stck0 falling edge clock these three bits are used to select the clock source for the stm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f sys is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 st0on : stm counter on/off control 0: off 1: on this bit controls the overall on/of f function of the stm. setting the bit high enables the counter to run, clearing the bit disables the stm. clearing this bit to zero will stop the counter from counting and turn of f the stm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the stm is in the c ompare ma tch out put mod e or t he pw m ou tput mod e or si ngle pul se out put mode then the stm output pin will be reset to its initial condition, as specifed by the st0oc bit, when the st0on bit changes from low to high. bit 2~0 st0rp2~ st0rp0 : stm ccrp 3-bit register, compared with the stm counter bit 9~bit 7 comparator p match period 000: 1024 stm clocks 001: 128 stm clocks 010: 256 stm clocks 011: 384 stm clocks 100: 512 stm clocks 101: 640 stm clocks 110: 768 stm clocks 111: 896 stm clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the st0cclr bit is set to zero. setting the st0cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu stm0c1 register bit 7 6 5 4 3 2 1 0 na ? e st0m1 st0m0 st0io1 st0io0 st0oc st0pol st0dpx st0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 st0m1~ st0m0 : select stm operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the stm. t o ensure reliable operation the st m shoul d be swi tched of f be fore a ny c hanges a re m ade t o t he st 0m1 a nd st0m0 bits. in the t imer/counter mode, the stm output pin state is undefned. bit 5~4 st0io1~ st0io0: select stm function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of stp0i 01: input capture at falling edge of stp0i 10: input capture at falling/rising edge of stp0i 11: input capture disabled timer/counter mode: unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the st0io1~st0io0 bits determi ne how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a . when the st0io 1~st0io0 bits a re b oth z ero, t hen no c hange wi ll t ake p lace on t he o utput. t he i nitial v alue of the tm output pin should be setup using the st0oc bit. note that the output level requested by the st0io1~st0io0 bits must be dif ferent from the initial value setup using the st0oc bit otherwise no change will occur on the tm output pin when a compare m atch o ccurs. aft er t he t m o utput pi n c hanges st ate i t c an b e re set t o i ts initial level by changing the level of the st0on bit from low to high. in the pwm mode, the st0io1 and st0io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the st0io1 and st0io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the st0io1 and st0io0 bits are changed when the tm is running.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu bit 3 st0oc : stm output control bit compare match output mode 0: initial low 1: initial high pwm output mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the stm output pin. its operation depends upon whether stm is being used in the compare match output mode or in the pwm output mode/ single puls e output mode. it has no ef fect if the stm is in the t imer/counter mode. in t he com pare ma tch out put mode i t de termines t he l ogic l evel of t he st m output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low . in the single pulse output mode it determines the logic level of the stm output pin when the st0on bit changes from low to high. bit 2 st0pol : stm output polarity control 0: non-invert 1: invert this bit controls the polarity of the stm output pin. when the bit is set high the stm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the stm is in the t imer/counter mode. bit 1 st0dpx : stm pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 st0cclr : select stm counter clear condition 0: stm comparator p match 1: stm comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard stm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the st0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the st0cclr bit is not used in the pwm output mode, single pulse or input capture mode. stm0dl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7 ~ 0 stm counter low byte register bit 7 ~ bit 0 stm 10-bit counter bit 7 ~ bit 0 stm0dh register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 stm counter high byte register bit 1 ~ bit 0 stm 10-bit counter bit 9 ~ bit 8
rev. 1.10 ? 4 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu stm0al register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stm ccra low byte register bit 7 ~ bit 0 stm 10-bit counter bit 7 ~ bit 0 stm0ah register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 stm ccra high byte register bit 1 ~ bit 0 stm 10-bit counter bit 9 ~ bit 8 standard type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the st0m1 and st0m0 bits in the stm0c1 register. compare output mode to select this mode, bits st0m1 and st0m0 in the stm0c1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the st0cclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both stma0f and stmp0f interrupt request fags for comparator a and comparator p respectively, will both be generated. if the st0cclr bit in the stm0c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the stma0f interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when st0cclr is high no stmp0f interrupt request flag will be generated. in the compare match output mode, the ccra can not be set to 0. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the stma0f interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the stm output pin, will change state. the stm output pin condition however only changes state when an stma0f interrupt request fag is generated after a compare match occurs from comparator a. the stmp0f interrupt request fag, g enerated f rom a c ompare m atch o ccurs f rom c omparator p , wi ll h ave n o e ffect o n t he st m output pin. the way in which the stm output pin changes state are determined by the condition of the st0io1 and st0io0 bits in the stm0c1 register . the stm output pin can be selected using the st 0io1 a nd st 0io0 bi ts t o go hi gh, t o go l ow or t o t oggle fr om i ts pre sent c ondition whe n a compare match occurs from comparator a. the initial condition of the stm output pin, which is setup afte r the st0on bit changes from low to high, is setup using the st0oc bit. note that if the st0io1 and st0io0 bits are zero then no pin change will take place.
rev. 1.10 ?4 de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ccra ccrp 0x?ff counte? ove?flow ccra int. flag stma0f ccrp int. flag stmp0f ccrp > 0 counte? ?lea?ed ?y ccrp value stm o/p pin st0on pause counte? reset output pin set to initial level low if st0oc = 0 output toggle with stma0f flag he?e st0io[1:0] = 11 toggle output sele?t now st0io[1:0] = 10 a?tive high output sele?t output not affe?ted ?y stma0f flag. re ?ains high until ?eset ? y st0on ?it compare match output mode - st0cclr = 0 st0cclr = 0; st0m[1:0] = 00 st0pau resu?e stop ti?e ccrp > 0 ccrp = 0 st0pol output pin reset to initial value output inve?ts when st0pol is high output ?ont?olled ?y othe? pin - sha?ed fun?tion counte? value compare match output mode C st0cclr=0 note: 1. w ith st0cclr = 0 a comparator p match will clear the counter 2. the tm output pin controlled only by the stma0f fag 3. the output pin reset to initial state by a st0on bit rising edge
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ccra ccrp 0x?ff ccra int. flag stmp0f ccrp int. flag stma0f ccra > 0 counte? ?lea?ed ?y ccra value stm o/p pin st0on pause counte? reset output pin set to initial level low if st0oc = 0 output toggle with stma0f flag he?e st0io[1:0] = 11 toggle output sele?t now st0io[1:0] = 10 a?tive high output sele?t output not affe?ted ?y stma0f flag. re ?ains high until ?eset ? y st0on ?it compare match output mode - st0cclr = 1 st0cclr = 1; st0m[1:0] = 00 st0pau resu?e stop ti?e ccra = 0 st0pol output pin reset to initial value output inve?ts when st0pol is high output ?ont?olled ?y othe? pin - sha?ed fun?tion counte? value output does not ?hange no stma0f flag gene?ated on ccra ove?flow ccra = 0 counte? ove?flow stmp0f not gene?ated compare match output mode C st0cclr=1 note: 1. w ith st0cclr = 1 a comparator a match will clear the counter 2. the tm output pin controlled only by the stma0f fag 3. the output pin reset to initial state by a st0on rising edge 4. the stmp0f fag is not generated when st0cclr = 1
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu timer/counter mode to se lect t his mode , bi ts st 0m1 and st 0m0 i n t he st m0c1 regi ster should be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the stm output pin is not used. therefore the above description and t iming diagrams for the compare match out put mod e c an be use d t o un derstand i ts fu nction. as t he st m ou tput pi n i s no t use d i n this mode, the pin can be used as a normal i/o pin or other pin-shared function by setting pin-share function register. pwm output mode to select this mode, bits st0m1 and st0m0 in the stm0c1 register should be set to 10 respectively and also the st0io1 and st0io0 bits should be set to 10 respectively . the pwm function within the stm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the stm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. in t he pw m out put m ode, t he st 0cclr bi t ha s no e ffect a s t he pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or dut y c ycle i s de termined usi ng t he st 0dpx bi t i n t he st m0c1 re gister. t he pw m wa veform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the st0oc bit in the stm0c1 register is used to select the required polari ty of the pwm waveform whi le the two st0io1 and st0io0 bi ts are used to enable the p wm output or to force the s tm output pin to a f xed high or low level. the st0pol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit stm, pwm output mode, edge-aligned mode, st0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 5 ? ? 84 51 ? ? 40 7 ? 8 89 ? 10 ? 4 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the stm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit stm, pwm output mode, edge-aligned mode, st0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra duty 1 ? 8 ? 5 ? ? 84 51 ? ? 40 7 ? 8 89 ? 10 ? 4 the pwm output period is determined by the ccra register value together with the stm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ccrp ccra counte? value counte? clea?ed ?y ccrp ccra int. flag stma0f ccrp int. flag stmp0f stm o/p pin (st0oc=1) st0on pwm duty cy?le set ?y ccra pwm pe?iod set ?y ccrp counte? stop if st0on ?it low counte? ?eset when st0on ?etu?ns high pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion ti?e st0dpx=0;st0m[1:0]=10 st0pol output inve?ts when st0pol = 1 st0pau resu?e pause stm o/p pin (st0oc=0) pwm output mode C st0dpx = 0 note: 1. here st0dpx = 0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when st0io[1:0] = 00 or 01 4. the st0cclr bit has no infuence on pwm operation
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ccra ccrp counte? value counte? clea?ed ?y ccra ccrp int. flag stmp0f ccra int. flag stma0f stm o/p pin (st0oc=1) st0on pwm duty cy?le set ?y ccrp pwm pe?iod set ?y ccra counte? stop if st0on ?it low counte? ?eset when st0on ?etu?ns high pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion ti?e st0dpx=1;st0m[1:0]=10 st0pol output inve?ts when st0pol = 1 st0pau resu?e pause stm o/p pin (st0oc=0) pwm output mode - st0dpx = 1 note: 1. here st0dpx = 1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when st0io[1:0] = 00 or 01 4. the st0cclr bit has no infuence on pwm operation
rev. 1.10 70 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 71 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu single pulse mode to select this mode, bits s t0 m1 and st0m0 in the stm0c1 register should be set to 10 respectively and also the st0io1 and st0io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the stm output pin. the t rigger f or t he p ulse o utput l eading e dge i s a l ow t o h igh t ransition o f t he st 0on b it, wh ich can be implement ed using the application program. however in the single pulse mode, the st 0 on bit can also be made to automatically change from low to high using the external stck0 pin, which will in turn initiate the single pulse output. when the st0on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the st0on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the st0on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. s/w co??and setst0on o? stck0 pin t?ansition t?ailing edge s/w co??and clrst0on o? ccra co?pa?e mat?h stp0 output pin pulse width = ccra value leading edge st0on ?it 0 1 st0on ?it 1 0 single pulse generation counte? value ccrp ccra st0on st0pau st0pol ccrp int. flag stmp0f ccra int. flag stma0f stm o/p pin (st0oc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when st0on ?etu?ns high st0m [1:0] = 10 ; st0io [1:0] = 11 pulse width set ?y ccra output inve?ts when st0pol = 1 no ccrp inte??upts gene?ated stm o/p pin (st0oc=0) stck0 pin softwa?e t?igge? clea?ed ?y ccra ?at?h stck0 pin t?igge? auto. set ?y stck0 pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the pulse is triggered by setting the st0on bit high 4. in the single pulse mode, st0io [1:0] must be set to 11 and can not be changed.
rev. 1.10 70 de?e??e? 1?? ?01? rev. 1.10 71 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu however a compa re match from comparator a will also automatically clear the st0on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a stm interrupt. the counter can only be res et back to zero w hen the st0o n bit changes from low to high w hen the counter restarts. in the single pulse mode ccrp is not used. the st0cclr and st0dpx bits are not used in this mode. capture input mode to select this mode bits st0m1 and st0m0 in the stm0c1 register should be set to 01 respectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the stp0i, whose active edge can be either a rising edge, a falling edge or both rising and fallin g edges; the active edge transition type is selected using the st0io1 and st0io0 bits in the stm0c1 register . the counter is started when the st0on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the stp0i the present value in the counter will be latched into the ccra registers and a stm interrupt generated. irrespective of what events occur on the stp0i the counter will continue to free run until the st0on bit changes from high to low . when a ccrp c ompare m atch oc curs t he c ounter wi ll re set ba ck t o z ero; i n t his wa y t he ccrp va lue can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a st m i nterrupt wi ll a lso b e g enerated. c ounting t he n umber o f o verfow i nterrupt signals from t he ccrp c an be a use ful m ethod i n m easuring l ong pul se wi dths. t he st 0io1 a nd st0io0 bits can select the active trigger edge on the stp0i to be a rising edge, falling edge or both edge types. if the st0io1 and st0io0 bits are both set high, then no capture operation will take place i rrespective of wha t happe ns on t he st p0i, howe ver i t m ust be note d t hat t he c ounter wi ll continue to run. the st0cclr and st0dpx bits are not used in this mode.
rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 7? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu counte? value yy ccrp st0on st0pau ccrp int. flag stmp0f ccra int. flag stma0f ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset st0m [1:0] = 01 stm ?aptu?e pin stp0i xx counte? stop st0io [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. st0m[1:0] = 01 and active edge set by the st0io[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the st0cclr and st0dpx bits are not used 4. no output function C st0oc and st0pol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains and sacs bit felds. note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly configured except the sains and sacs bit fie lds. more det ailed i nformation a bout t he a/ d i nput si gnal i s desc ribed i n t he a/d converter control registers and a/d converter input signal sections respectively. input channels a/d channel select bits input pins 5+ ? sains ? ~sains0 ? sacs ? ~sacs0 an0~an ? and vsense vbg ? 10is the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. pin-sha?ed sele?tion sacs?~sacs0 sains?~sains0 a/d converter start adbz enadc v ss a/d clo?k ? n (n=0~7) f sys sacks?~ sacks0 v dd enadc sadol sadoh vsense an0 an? a/d refe?en?e voltage a/d data registe?s v bg 10is adrfs savrs?~ savrs0 v ref v dd pin-sha?ed sele?tion a/d converter structure
rev. 1.10 74 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 75 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 sadol(adrfs=0) d ? d ? d1 d0 sadol(adrfs=1) d7 d ? d5 d4 d ? d ? d1 d0 sadoh(adrfs=0) d11 d10 d9 d8 d7 d ? d5 d4 sadoh(adrfs=1) d11 d10 d9 d8 sadc0 start adbz enadc adrfs sacs ? sacs ? sacs1 sacs0 sadc1 sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 a/d converter data registers C sadol, sadoh as the device contains an internal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompanying table. d0~d1 1 are the a/d conversion result data bits. any un used bi ts wi ll be re ad a s z ero. not e t hat t he a/ d c onverter da ta re gister c ontents wi ll be unchanged to zero if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d ? d5 d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d ? d5 d4 d ? d ? d1 d0 a/d data registers a/d converter control registers C sadc0, sadc1, pasr to control the function and operation of the a/d converter , several control registers known as sadc0 and sadc1 are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter , the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter busy status. the sacs 3 ~sacs0 bits in the sadc0 register are used to determine which external channel input is selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. if the sains2~sains0 bits are set to 000, the external analog channel input is selected to be converted and the sacs 3 ~sacs0 bits can determine which external channel is selected to be converted. if the sains2~sains0 bits are set to 001, the v bg voltage is selected to be converted. if the sains2~sains0 bits are set to 01 0 , the op a output voltage is selected to be converted. the internal analog signals can be derived from the a/d converter supply power , v dd , or internal reference voltage, v ref . if the internal analog signal is selected to be converted, the external channel signal input will automatically be switched off to avoid the signal contention. the pin-shared function control register , named p asr, contain s the corresponding pin-shared selection bits which determine which pins on port a are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors conn ected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.10 74 de?e??e? 1?? ?01? rev. 1.10 75 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu sadc0 register bit 7 6 5 4 3 2 1 0 na ? e start adbz enadc adrfs sacs ? sacs ? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 0 1 0: start a/d conversion 0 1: reset the a/d converter and set adbz to 0 1 0: start a/d conversion and set adbz to 1 bit 6 adbz : adc busy fag 0: a/d conversion ended or no conversion 1: a/d is busy bit 5 enadc : adc enable/disable control register 0: adc disable 1: adc enable bit 4 adrfs : a/d output data format selection bit 0: adc output data format sadoh=d[11:4]; sadol=d[3:0] 1: adc output data format sadoh=d[11:8]; sadol=d[7:0] bit 3~0 sacs 3~sacs0 : adc input channels selection 000 0: adc input channel comes from an0 00 01: adc input channel comes from an1 00 10: adc input channel comes from an2 0 011: adc input channel comes from an3 0 100: adc input channel comes from vsense other values : adc input is foating sadc1 register bit 7 6 5 4 3 2 1 0 na ? e sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 sains2~sains0 : internal adc input channel selection bit 000: adc input only comes from external pin 001: adc input also comes from v bg 010: adc input also comes from 10 is 011: gnd 100: gnd 101: the same as 000 110: the same as 000 111: the same as 000 bit 4~3 sa vrs1~sa vrs0 : adc reference voltage selection 00: reference voltage only comes from v ref 01: reference voltage only comes from v dd 10: the same as 00 11: the same as 00 note: when select v ref as adc reference voltage, the pin share control bits (p as2, pas1) is (1, 0) to select vref as input. bit 2~0 sacks2~sacks0 : adc clock rate selection bit 000: f sys 001: f sys / 2 010: f sys / 4 011: f sys / 8 100: f sys / 16 101: f sys / 32 110: f sys / 64 111: f sys /128
rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 77 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu a/d operation the st art bit is used to start and reset the a/d converter . when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the st art bit is brought from low to high but not low again, the adbz bit in the sadc0 register will be cleared to zero and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in process or not. when the a/d converter is reset by setting the st art bit from low to high, the adbz fag will be cleared to 0. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleare d to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program fow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. although the a /d clock s ource is determined by the s ystem clock f sys , and by bits s acks2~ sacks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended value of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the sacks2~sacks0 bits should not be set to 000b or 11xb. doing so will give a/d clock periods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d c lock period which may result in inaccurate a/d conversion values. controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he enadc bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the e nadc b it i s se t h igh t o p ower o n t he a/ d c onverter i nternal c ircuitry a c ertain d elay, a s indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by confguring the corresponding pin-shared control bits, if the enadc bit is high then some power will still be consumed. in power conscious applications it is therefore recom mended that the enadc is set low to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the internal adc power or from an external reference sources supplied on pin vref voltage. the desired selection is made using the sa vrs 1 ~ sa vrs0 bits. as the vref pin is pin-shared with other functions, when the vref pin is selected as the reference voltage supply pin, the vref pin-shared function control bits should be properly confgured to disable other pin functions.
rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 77 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu a/d converter input signal all of the a/ d analog input pins are pin-shared with the i/o pins on port a as well as other functions. the corredponding selection bits for each i/o pin in the p asr register , determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the pin-shared function control bits confgure its corresponding pin as an a/d analog channel input, the pin will be setup to be an a/d converter external channel input and the original pin functions disabled. in this way , pins can be changed under program control to change their function between a/d inputs and other function s. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac port control register to enable the a/d input as when the pin-shared function control bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the sa vrs[ 1 :0] in the sadc1 register. the analog input values must not be allowed to exceed the value of v ref. conversion rate and timing diagram a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversi on. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. t herefore a total of 16 a/ d clock cycles for an a/ d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period / 16 however, there is a usage limitation on the next a/d conversion after the current conversion is complete. when the current a/d conversion is complete, the converted digital data will be stored in the a/d data register pair and then latched after half an a/d clock cycle. if the start bit is set to 1 in half an a/d clock cycle after the end of a/d conversion, the converted digital data stored in the a/d data register pair will be changed. therefore, it is recommended to initiate the next a/d conversion after a certain period greater than half an a/d clock cycle at the end of current a/d conversion. enadc start adbz sacs[?:0] off on off on t on?st t ads a/d sa?pling ti?e t ads a/d sa?pling ti?e sta?t of a/d ?onve?sion sta?t of a/d ?onve? sion sta?t of a/d ?onve?sion end of a/d ?onve?sion end of a/d ?onve?sion t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e 0011b 0010b 0000b 0001b a/d ?hannel swit?h a/d conversion timing
rev. 1.10 78 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 79 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion frequency by sacks2~ sacks0 ? step 2 enable the adc by set enadc=1 ? step 3 select which pins will be confgure as adc analog inputs ? step 4 if input comes from i/o, set sains[2:0]=000 and then set sacs bit felds to corresponding p a input if input comes from internal input, set sains[2:0] to corresponding internal input source ? step 5 select reference voltage comes from external v ref or v dd by savrs[ 1:0] note: if select v ref as reference voltage, (pas2, pas1) = (1, 0) ? step 6 select adc output data format by adrfs ? step 7 if adc interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bits, ade, must both set high in advance. ? step 8 the a/d converter procedure can now be initialized by set start from low to high and then low again ? step 9 if adc is under conversion, adbz=1. after a/d conversion process is completed, the adbz fag will go low , and then output data can be read from sadoh and sadol registers. if the adc i nterrupt i s enabl ed and the st ack i s not ful l, dat a can be ac quired by int errupt servic e program. another way to get the a/d output data is polling the adbz fag.
rev. 1.10 78 de?e??e? 1?? ?01? rev. 1.10 79 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry c an b e swi tched o ff t o r educe p ower c onsumption, b y c learing t he e nadc b it i n t he sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contains a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.

? ? ? ? ? ? ?? ? ?
? ideal a/d transfer function
rev. 1.10 80 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 81 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an adbz polling method to detect the end of conversion clr a de ; disable adc interrupt mov a,0 3 h mov sa dc1,a ; select f sys /8 as a/d clock and switch off the bandgap reference ; voltage mov a,0 1 h ; setup pasr to confgure pin an0 mov p asr,a mov a, 0 0h mov s adc0,a ; enable and connect an0 channel to a/d converter set e nadc : start_conversion: clr st art ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz a dbz ; poll the sadc0 register adbz bit to detect end of a/d conversion jmp p olling_eoc ; continue polling mov a ,sadol ; read low byte conversion result value mov s adol_buffer,a ; save result to user defned register mov a ,sadoh ; read high byte conversion result value mov s adoh_buffer,a ; save result to user defned register : : jmp s tart_conversion ; start next a/d conversion
rev. 1.10 80 de?e??e? 1?? ?01? rev. 1.10 81 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu example: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a,0 3 h mov sa dc1,a ; select f sys /8 as a/d clock and switch off the bandgap reference ; voltage mov a,0 1 h ; setup pasr to confgure pin an0 mov p asr,a mov a, 0 0h mov s adc0,a ; enable and connect an0 channel to a/d converter set e nadc start_conversion: clr st art ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d clr a df ; clear adc interrupt request fag set a de ; enable adc interrupt set e mi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov ac c_stack,a ; save acc to user defned memory mov a ,status mov s tatus_stack,a ; save status to user defned memory : : mov a ,sadol ; read low byte conversion result value mov s adol_buffer,a ; save result to user defned register mov a ,sadoh ; read high byte conversion result value mov s adoh_buffer,a ; save result to user defned register : : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore status from user defned memory mov a ,acc_stack ; restore acc from user defned memory reti
rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 8? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu battery charge module the device contains a battery char ge module which consists of the battery char ging constant current(cc) or constant voltage(cv) modes and the ovp/ocp functions. the constant current signal is from isense pin while the constant voltage signal is from vsense pin. the ovp or ocp circuitry u ses r espectively t he e xternal p ins, n amed vse nse, i sense, a nd c p0n, t o d etect 1 0 is voltage or vs voltage and this output voltage is used to modify the duty of the current mode pwm controller to control the charging current and charging voltage. rectifier/ filter/ regulator 10xis vs sensein current mode pwm controller dac isense 3v 5v pgd a1n a1x opa0 opa1 ovp ocp bat. 5v cp0n vsense ch1 ch0 9r r hv mux battery charge module structure note: 1. the input voltage range of isense should be less than 0.36v at 5v. 2. when vsense voltage is more than 3v and v dd is more than or equal to 4.6v , ovp output is high, the ocvp interrupt occurs and a1x pin output low level. 3. when 10 is v oltage is more than cp0n and v dd is more than or equal to 4.6v , ocp output is high, the ocvp interrupt occurs and a1x pin output low level. battery charg ing constant current and constant voltage modes the battery char ging current is mea sured using a resistor to produce a voltage which is input to the opa0 via isense pin. then the isense voltage is amplifed 10 times by an op a0 to produce 10 is voltage. this voltage is input to a mux channel 1 and adc internal channel. when mux selec t ch1 from the 10 is voltage and op a1 positive voltage from dac, if the 10 is voltage is less than dac voltage, a1x output signal is transmitted to current mode pwm controller via a phot o-coupler t o i ndirectly i ncrease pw m dut y c ycle of t he powe r mos dri ving port of t he current mode pwm control circuits. the batte ry char ging voltage is mea sured using external two resistors to produce a voltage which is input to the mux via vsense pin. this voltage is the same as vs. when mux channel select ch0, the vs voltage will be sent out via sensein pin and external resister to the op a1 negative input. if opa1 positive from 8-bit dac input, decide dac value as decide battery charging voltage, because a1x of op a1 out put i s t ransmitted vs a nd dac di fference vi a a phot o-coupler t o c urrent m ode pwm controller , if vs voltage is less than dac voltage, a1x is transmitted to current mode pwm controller via a photo-coupler to indirectly increases pwm duty cycle of the power mos driving port of the current mode pwm control circuits.
rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ocp and ovp functions the ocp function is used to monitor the battery char ging current, which is converted to a voltage using a resistor , and the voltage signal is input to the op a0 via the isense pin. then the isense voltage is amplife d 10 times by an op a0 to produce 10 is voltage. if 10 is voltage is more than cp0n and pgd(p ower good detection) detects that the device power supply is ready , v dd is more than or equal to 4.6v , the ocvp interrupt will occur when corresponding interrupt is enabled and will force a1x output low. the ovp function is used to monitor the battery char ging voltage, which is converted to a voltage using external two resistors, and the voltage is input to the vsense pin. if the vsense pin input voltage is more than 3v and pgd(power good detection) detects that the device power supply is re ady, v dd is more than and equal to 4.6v , the ocvp interrupt will oc cur when corresponding interrupt is enabled and will force a1x output low. battery charge module registers as the battery char ge module is complex, the overall function is controlled by several registers and the corresponding register defnitions are described in the accompanying sections. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chrgen chgen7 chgen ? chgen5 chgen4 chgen ? chgen ? chgen1 chgen0 dac8 d7 d ? d5 d4 d ? d ? d1 d0 dacc endac sensw muxs5 muxs4 muxs ? muxs ? muxs1 muxs0 a0vos a0fm a0rsp a0x a0of4 a0of ? a0of ? a0of1 a0of0 pgdr pgdf chrgen register bit 7 6 5 4 3 2 1 0 na ? e chgen7 chgen ? chgen5 chgen4 chgen ? chgen ? chgen1 chgen0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 chgen7~chgen0 : mux, dac and opa0 related control registers modifcation 10101010 : the related registers could be modifed other values : ignore registers modify when these bits are changed to any other values except 10101010, the dac8, dacc, sensw and a0vos registers cannot be modifed.
rev. 1.10 84 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 85 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu digital to analog converter the ba ttery c harge m odule contains a n 8-b it dac. the dac i s use d t o se t a re ference c harging current or reference charging voltage using dac8 register. d[7:0] r?r 8 bit dac endac s0 - + opa 1 vdd pa 5/a1p dac 0 note : 1. the endac has interlocking relationships with s0 when endac=0, dac disable and s0 o ff . when endac=1, dac enable and s0 on. 2. opa1 positive input voltage can be selected from external pin, which is named a1p . dac8 register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 0 0 0 bit 7~0 d7~d0 : dac output control code the dac output voltage is calculated using the following equation: 8-bit dac output voltage = 8 8[7 : 0] 2 dd dac v ? ? ? ? ? ? dacc register bit 7 6 5 4 3 2 1 0 na ? e endac r/w r/w por 1 bit 7 endac : dac and s 0 control 0 : dac disable&s0 off 1: dac enable&s0 on bit 6 ~0 unimplemented, read as 0
rev. 1.10 84 de?e??e? 1?? ?01? rev. 1.10 85 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu sensw register bit 7 6 5 4 3 2 1 0 na ? e muxs5 muxs4 muxs ? muxs ? muxs1 muxs0 r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 bit 7~ 6 unimplemented, read as 0 bit 5 ~0 muxs5~muxs0 : mux channel selection 0 10101: ch0 (switch to vsense pin input) 101010: ch1 (switch to opa0 input) other values: keep the current switch state unchanged. for example, when the mux[5:0]=101010, switch to ch1, but when mux[5:0] are changed to 1 11111, switch state, ch1, is unchanged, till when the mux[5:0] is set to 010101, switch state will be changed to ch0. operational amplifer 0 the battery charge module contains an operational amplifer 0, which only plays a role in the battery charging constant current mode. - + v dd =5v ?v( ovp ) 0.1v isense vm s0 s1 s? 9r r opa 0 ch 1 ch 0 a0 fm a0x a0vos register bit 7 6 5 4 3 2 1 0 na ? e a0fm a0rsp a0x a0of4 a0of ? a0of ? a0of1 a0of0 r/w r/w r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 a0fm : operational amplifer mode or offset calibration mode 0 : operational amplifer mode (s1 off and s2 on) 1: offset calibration mode (s1 on and s2 off) bit 6 a0rsp : operational amplifer input voltage selection bit 0: input voltage comes from isense pin 1: input voltage comes from internal vm reference voltage bit 5 a0x : operational amplifer output; positive logic. this bit is read only. bit 4 ~0 a0of4~a0of0 : operational amplifer offset calibration data bits
rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 87 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu opa0 functions the op a0 can operate together with the mux, dac and op a1 as shown in the main functional blocks of the battery charging circuit. the op a0 provides its input voltage of fset to be adjustable by using common mode input to calibrate the offset. the calibration steps are as following: ? 1. set a0fm=1 to setup the offset calibration mode, here s1 on and s2 off. ? 2. set a0rsp to select which input pin is to be used as the reference voltage C isense pin or vm. ? 3. adjust a0of4~a0of0 until the output status changes ? 4. set a0fm = 0 to restore the normal mode. note: 1. when calibration, the device can detect the opa output status by a0x bit. 2. vm voltage is 0.1v at v dd = 5 v. 3. after opa0 offset calibration, set the a0rsp bit by the actual applications. ? pgdr register bit 7 6 5 4 3 2 1 0 na ? e pgdf r/w r por 0 bit 7~ 1 unimplemented, read as 0 bit 0 pgdf : power good detection ready fag 0 : detect v dd <4.6v 1: detect v dd 4.6v note: the device can detect the v dd current status by pgdf bit.
rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 87 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the m icrocontroller t o d irect a ttention t o t heir r espective n eeds. t he d evice c ontains one e xternal interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int pin, while the internal interrupts are generated by various internal functions such as the tm, t ime base, eeprom , ovcp and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc1 registers which setup the primary interrupt, the second is the mfi0 registe r whi ch se tup t he mult i-function i nterrupts. fi nally t here i s a n int eg registe r t o setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble individual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo ? al emi int pin inte intf ti ? e base tbne tbnf n=0 o ? 1 multi-fun ? tion mf0e mf0f ocv p fun ? tion ocvpf ocvpe eeprom dee def a/d conve ? te ? ade adf tm stma0e stma0f stmp0e stmp0f interrupt register bit naming conventions interrupt register contents name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ ints1 ints0 intc0 mf0f tb0f intf mf0e tb0e inte emi intc1 tb1f adf def ocvpf tb1e ade dee ocvpe mfi0 stma0f stmp0f stma0e stmp0e
rev. 1.10 88 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 89 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu integ register bit 7 6 5 4 3 2 1 0 na ? e ints1 ints0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ints1, ints0 : defne int interrupt active edge 00: disable interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt intc0 register bit 7 6 5 4 3 2 1 0 na ? e mf0f tb0f intf mf0e tb0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mf0f : multi-function 0 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : t ime base 0 interrupt request flag 0: no request 1: interrupt request bit 4 intf : int interrupt request flag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 inte : int interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.10 88 de?e??e? 1?? ?01? rev. 1.10 89 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu intc1 register bit 7 6 5 4 3 2 1 0 na ? e tb1f adf def ocvpf tb1e ade dee ocvpe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t ime base 1 interrupt request flag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 ocvpf : ocvp interrupt request flag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 ocvpe : ocvp interrupt control 0: disable 1: enable mfi0 register bit 7 6 5 4 3 2 1 0 na ? e stma0f stmp0f stma0e stmp0e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 stma0f : stm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 stmp0f : stm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 stma0e : stm comparator a match interrupt control 0: disable 1: enable bit 0 stmp0e : stm comparator p match interrupt control 0: disable 1: enable
rev. 1.10 90 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 91 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter addres s from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.10 90 de?e??e? 1?? ?01? rev. 1.10 91 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu int pin ti?e base 0 intf tb 0f inte tb 0e emi 04 h emi 08 h eeprom def dee 10h 0 ch 14 h 18 h 1 ch inte??upt na?e request flags ena?le bits maste? ena?le vector emi auto disa?led in isr p?io?ity high low ti?e base 1 tb 1f tb 1e inte??upts ?ontained within multi - fun?tion inte??upts xxe ena?le bits xxf request flag ? auto ?eset in isr legend xxf request flag ? no auto ?eset in isr emi emi emi stm p stmp0f stmp0e stm a stma0f stma0e emi emi ocvp ocvpf ocvpe m. fun?t . 0 mf0f mf0e a/d adf ade inte??upt na?e request flags ena?le bits interrupt structure external interrupt the external interrupt is controlled by signal transitions on the int pin. an external interrupt request will take place when the external interrupt request fag, intf , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to the interrupt vector address, the global interrupt enable bit, emi, and the extern al interr upt enable bit, inte, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, it can only be confgured as extern al interru pt pin by setting the pin-shared registers. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request flag, intf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that the pull-high resistor selection on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 9? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu multi-function interrupt within t h i s de vice t here is o ne mult i-function i nterrupt. unli ke t he ot her i ndependent i nterrupts, this interrupt ha s no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request fag, mf0f are set. the multi-function interrupt fag will be set when any of their included functions generate an interr upt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within the multi-function interrupt occurs, a subroutine call to one of the multi- function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fa g, wi ll be aut omatically reset a nd t he emi bi t wi ll be aut omatically c leared t o di sable other interrupts. however, it must be noted that, although the multi-function interrupt flag will be automatically reset when the interrupt is serviced , the request fag from the original source of the multi-function interrupts, namely the tm interrupt s, will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the device contai ns an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termin ation of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the inte rrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converte r interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt flag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.
rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu tbc register bit 7 6 5 4 3 2 1 0 na ? e tbon tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : tb0 and tb1 control bit 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb1 1 ~ tb10 : select t ime base 1 t ime-out period 00: 2 12 /f tb 01: 2 13 /f tb 10: 2 14 /f tb 11: 2 15 /f tb bit 3 unimplemented, read as "0" bit 2~0 tb02 ~ tb00 : select t ime base 0 t ime-out period 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 11 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 14 /f tb 111: 2 15 /f tb

time base interrupt eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the eeprom interrupt request fag, def, will also be automatically cleared.
rev. 1.10 94 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 95 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu tm interrupts the t m ha s t wo i nterrupts. all of t he t m i nterrupts a re c ontained wi thin t he mul ti-function interrupt. for the tm there are two interrupt request fag s tmp0f and s tma0f and two enable bits s tmp0e and s tma0e. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit, mf0e, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mf0f fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. ocvp interrupt the ocvp interrupt is controlled by the two internal comparators. an ocvp interrupt request will take pl ace whe n t he oc vp i nterrupt re quest fa g, oc vpf, i s se t, a si tuation t hat wi ll oc cur whe n the comparators output changes state. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and ocvp interrupt enable bit, ocvpe, must frst be set. when the interrupt is enabled, the stack is not full and the comparator input generates a comparator output transition, a subroutine call to the ocvp interrupt vector , will take place. when the ocvp interrupt is serviced, the emi bit will be automatically clear ed to disable other interrupts, and the ocvp interrupt request fag, ocvpf, will also be automatically cleared. interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function.
rev. 1.10 94 de?e??e? 1?? ?01? rev. 1.10 95 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mf0f , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 97 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a l ow vo ltage c ondition wi ll be de termined. a l ow vo ltage c ondition i s i ndicated whe n t he l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the enl vd bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 na ? e lvdo enlvd vbgen vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 enlvd : low v oltage detector control 0: disable 1: enable bit 3 vbgen : bandgap buffer control 0: disable 1: enable bit 2~0 vlvd2~vlvd0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 97 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu lvd operation the low v oltage detector function operates by comparing the power supply voltage, vdd, with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when t he power suppl y vol tage, vdd, fa lls be low t his pre -determined va lue, t he l vdo bi t wi ll be set high indica ting a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled.when the device is under the sleep mode, the low voltage detector will disable, even if the enl vd bit is high. after enabling the low v oltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading t he l vdo bi t. note a lso t hat a s t he vdd vol tage m ay ri se a nd fa ll ra ther sl owly, a t t he voltage nears that of vl vd, there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt, providing an alte rnative means of low voltage detection, in addit ion to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is in sleep mode the low v oltage detector will disable, even if the enlvd bit is high.
rev. 1.10 98 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 99 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu application circuit vsense vdd vss a/d vdd i/o i/o 0.1f tm voltage signal key mat?ix cont?ol devi?e pwm a1x analog signals photo ?ouple? cu??ent signal dac 10xis ovp ocp cp0n
rev. 1.10 98 de?e??e? 1?? ?01? rev. 1.10 99 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.10 100 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 101 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction set . as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.10 100 de?e??e? 1?? ?01? rev. 1.10 101 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov addm a ? [ ? ] add acc to data me ? o ? y 1 note z ? c ? ac ? ov add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 note z ? c ? ac ? ov sub a ? x su ? t ? a ? t i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov sub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov subm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 note z ? c ? ac ? ov sbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov sbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 note z ? c ? ac ? ov daa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 note c logic operation and a ? [ ? ] logi ? al and data me ? o ? y to acc 1 z or a ? [ ? ] logi ? al or data me ? o ? y to acc 1 z xor a ? [ ? ] logi ? al xor data me ? o ? y to acc 1 z andm a ? [ ? ] logi ? al and acc to data me ? o ? y 1 note z orm a ? [ ? ] logi ? al or acc to data me ? o ? y 1 note z xorm a ? [ ? ] logi ? al xor acc to data me ? o ? y 1 note z and a ? x logi ? al and i ?? ediate data to acc 1 z or a ? x logi ? al or i ?? ediate data to acc 1 z xor a ? x logi ? al xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 note z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement inca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc 1 z inc [ ? ] in ?? e ? ent data me ? o ? y 1 note z deca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] de ?? e ? ent data me ? o ? y 1 note z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 none rr [ ? ] rotate data me ? o ? y ? ight 1 note none rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 note c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 none rl [ ? ] rotate data me ? o ? y left 1 note none rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 note c
rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 10? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 none mov [ ? ] ? a move acc to data me ? o ? y 1 note none mov a ? x move i ?? ediate data to acc 1 none bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 note none set [ ? ].i set ? it of data me ? o ? y 1 note none branch jmp add ? ju ? p un ? onditionally ? none sz [ ? ] skip if data me ? o ? y is ze ? o 1 note none sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 note none sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 note none snz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 note none siz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o 1 note none sdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o 1 note none siza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none sdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none call add ? su ?? outine ? all ? none ret retu ? n f ? o ? su ?? outine ? none ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? none reti retu ? n f ? o ? inte ?? upt ? none table read tabrd [ ? ] read table (specifc page) to tblh and data memory ? note none tabrdc [ ? ] read ta ? le ( ? u ?? ent page) to tblh and data me ? o ? y ? note none tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? note none miscellaneous nop no ope ? ation 1 none clr [ ? ] clea ? data me ? o ? y 1 note none set [ ? ] set data me ? o ? y 1 note none clr wdt clea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt1 p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt ? p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 note none swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 none halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the t o and pdf flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.10 104 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 105 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.10 104 de?e??e? 1?? ?01? rev. 1.10 105 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 107 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 107 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.10 108 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 109 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.10 108 de?e??e? 1?? ?01? rev. 1.10 109 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.10 110 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 111 de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.10 110 de?e??e? 1?? ?01? rev. 1.10 111 de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 11 ? de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? HT45F5Q charger flash mcu HT45F5Q charger flash mcu 16-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ??? bsc b 0.154 bsc c 0.01 ? 0.0 ? 0 c 0. ? 90 bsc d 0.0 ? 9 e 0.050 bsc f 0.004 0.010 g 0.01 ? 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a ? bsc b ? .9 bsc c 0. ? 1 0.51 c 9.9 bsc d 1.75 e 1. ? 7 bsc f 0.10 0. ? 5 g 0.40 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.10 114 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 pb de?e??e? 1?? ?01? HT45F5Q charger flash mcu HT45F5Q charger flash mcu copy ? ight ? ? 01 ? ? y holtek semiconductor inc. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e a ?? u ? ate at the ti ? e of pu ? li ? ation. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that su ? h appli ? ations will ? e suita ? le without fu ? the ? ? odifi ? ation ? no ? ? e ? o ?? ends the use of its p ? odu ? ts fo ? appli ? ation that ? ay p ? esent a ? isk to hu ? an life due to ? alfun ? tion o ? othe ? wise. holtek's p ? odu ? ts a ? e not autho ? ized fo ? use as ?? iti ? al ? o ? ponents in life suppo ? t devi ? es o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek. ? o ? .tw.

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